In semiconductor fabrication technology, numerous active devices are built on a substrate and to enable these devices to function, interconnections between the devices formed of an electrically conductive material must be provided to either connect the devices between themselves or connect to an outside circuit. In the process of building electrically conductive interconnects, insulation must be provided between the interconnects such that they do not short with each other. The building of insulation layers in a semiconductor device can be performed by various deposition or growth techniques. For instance, an insulation layer of silicon oxide can be formed by a thermal oxidation technique, a plasma enhanced chemical vapor deposition (PECVD) of TEOS oxide technique, a PECVD silane oxide technique, an atmospheric pressure chemical vapor deposition (APCVD) technique, a PECVD TEOS-N.sub.2 O technique and other suitable techniques.
The thermal oxidation technique can be used at different stages of an integrated circuit fabrication process for various purposes such as to terminate silicon bonds at a silicon surface, to isolate conductors and semiconductors, or to provide a high quality dielectric for semiconductor gates, memory cell nodes, or capacitors. The thermal oxidation method is also used to grow a sacrificial oxide film that can be removed after fulfilling its purpose. For instance, to create a step in silicon for mask alignment, to remove a certain amount of silicon that was damaged, or to serve as a screen that blocks the penetration of unwanted dopant. The thermal oxidation process can be performed by subjecting a silicon wafer to an oxidizing ambient at elevated temperatures. One of the objectives in designing an oxidizing system is the capability of providing a high quality SiO.sub.2 film of uniform thickness while maintaining a low thermal budget (the product of temperature and time). Two common methods are used to grow thermal oxides of silicon, i.e., by dry oxygen and by water vapor. In both methods, silicon can be consumed and converted into SiO.sub.2.
The chemical vapor deposition technique has been used for growing silicon dioxide films in the semiconductor fabrication industry. SiO.sub.2 films can be deposited by a CVD method at temperatures as low as 400.degree. C. without affecting the silicon in the substrate. The deposition temperature can be further reduced in a plasma enhanced CVD method. The oxide film properties can be controlled by the deposition and annealing conditions to fit a specific usage for the film. For instance, when used as an insulating film between conducting layers, the outside layer can be deposited in an undoped condition and then annealed to improve its density and its dielectric properties at elevated temperatures. In other applications, the oxide film can be used as a diffusion or implantation mask to prevent outdiffusion of dopants from an underlying doped film. A commonly used method to deposit silicon oxide by the chemical vapor deposition method is to oxidize silane with oxygen at low pressure and low temperature, i.e., below 450.degree. C., or by decomposing tetraethoxysilane (TEOS) with or without oxygen at low pressure and at a higher temperature of approximately 700.degree. C. Silicon oxide films can also be formed by the reaction of silane with nitrous oxide (N.sub.2 O) during which stoichiometric silicon oxide or silicon-rich oxide can be produced by varying the N.sub.2 O/SiH.sub.4 ratio. Silicon oxide films can also be produced by reacting TEOS with ozone in an APCVD technique at a low reaction temperature range of 200.degree. C..about.400.degree. C.
In a typical silane oxidation process, silane reacts with oxygen at temperatures below 500.degree. C. to produce silicon dioxide and hydrogen. The process can be performed at low pressure and low temperature which enables the oxide film to be deposited over metals that have a low melting temperature such as aluminum and copper. The drawback of the method, however, is that the film deposited is not stoichiometric and therefore exhibits poor dielectric property and step coverage. The silane oxidation process is therefore typically used in a passivation step after metal deposition, or in combination with other insulating films. Silane or dichlorosilane can be reacted with nitrous oxides to form stoichiometric oxide films by reacting with an excess of N.sub.2 O at a higher reaction temperature, i.e., between about 700.degree. C..about.900.degree. C. The use of this process is limited since the temperature range exceeds the melting temperature of most metals used in the interconnects.
In a typical TEOS oxide process, an inert carrier gas such as nitrogen is bubbled through liquid TEOS to provide a gas mixture of TEOS in the reaction chamber and, subsequently it decomposes at a temperature between 650.degree. C..about.800.degree. C. to produce silicon oxide and other organic byproducts. The deposition rate of the TEOS oxide film depends on the partial pressure of TEOS in the gas mixture and the reaction temperature. The TEOS chemical vapor deposition method produces films of good uniformity and step coverage. However, its requirement of high reaction temperature precludes its use over low melting temperature metal layers.
A TEOS-ozone method can be carried out in an APCVD process at reaction temperature as low as 250.degree. C. by reacting TEOS with ozone. The oxide produced has good step coverage even in high aspect-ratio trenches or holes between metal lines. The technique is therefore more suitable for depositing oxide layers for insulating metal interconnects.
When an oxide film produced by the TEOS-ozone technique is used for insulating metal interconnects as an inter-metal dielectric (IMD) layer, it is frequently deposited on a thermal oxide or a PECVD TEOS oxide underlayer. The growth of the TEOS-ozone layer has a high pattern sensitivity (or surface sensitivity). The surface sensitivity of the oxide layer to its underlayer greatly affects the quality of the oxide film produced. For instance, when deposited on a silicon wafer, the thickness of the film can vary greatly at different locations on the wafer. FIGS. 1A and 1B show a trace made from scanning electron micrographs of a cross-section of a silicon wafer at a center portion 10 and at a middle portion 20, respectively. The TEOS-ozone oxide layers 12 and 14 are deposited over a PE oxide layer 26, metal interconnects 16 and an oxide layer 18 of BPSG or PSG. The PE-oxide layer 26 can be either a PE TEOS oxide layer or a PE silane oxide. The non-uniform thickness of the layers 12 and 14 is caused by the non-uniformity in the deposition rates achieved at different regions on the wafer surface, i.e., at the wafer center, middle region or the edge. As shown in FIG. 1A, the top surface 22 of the oxide layer 12 is more smooth when compared to the top surface 24 of the oxide layer 14 shown in FIG. 1B. The slower deposition rate at the wafer middle region results in poor surface coverage and deep trenches 28 formed in the surface 24. The deep trenches 28 cannot be eliminated by a subsequent planarization process, i.e., a chemical mechanical polishing (CMP) process or a spin-on glass (SOG) process. This results in voids and porosity in the device formed on the semiconductor substrate and consequently, defective products and lower throughput rate.
An illustration of the effect of different underlayers on the deposition rates is shown in FIGS. 2A and 2B. The percent change in deposition rate is shown for TEOS-ozone oxide deposition on a bare silicon surface (used as control, or 100%), a thermal oxide surface, a PECVD TEOS oxide surface, a PECVD SiH.sub.4 oxide surface, and a PECVD TEOS-N.sub.2 O oxide surface. It is seen in FIG. 2A that when an oxide layer is deposited on an underlayer of thermal oxide film, the deposition rate for the oxide is reduced by 60%. When the oxide layer is deposited on an underlayer of PECVD TEOS oxide film, the deposition rate is reduced by 15%. However, no degradation in the deposition rate is seen for the TEOS-ozone oxide when it is deposited on underlayers of either a PECVD SiH.sub.4 oxide layer or a PECVD TEOS-N.sub.2 O oxide layer.
FIG. 2B is a bar graph showing the effect of underlayers on the wet etch rates of TEOS-ozone oxide films. The wet etch rate ratio (compared to the control of a bare silicon surface) for the oxide films deposited on a thermal oxide layer, a PECVD TEOS oxide layer, a PECVD SiH.sub.4 oxide layer, and a PECVD TEOS-N.sub.2 O oxide layer are shown. It is seen that when the oxide layer is deposited on either a thermal oxide layer or a PECVD TEOS oxide layer, the wet etch rate increases by almost an order of magnitude. The drastic increase in the wet etch rate is an indication that the oxide layers formed have poor film quality (or high porosity) which is likely to produce defective products due to the potential of shorting.
A typical oxide deposition process is shown in FIGS. 3A-3C. As shown in FIG. 3A, a semiconductor device 30 is provided which has metal interconnects 34 formed on an insulating BPSG layer 36. The metal interconnects 34 have an anti-reflective coating layer 38 deposited on top to facilitate the photolithiography process. The interconnects 34 are deposited of a suitable metallic material such as aluminum, copper, tungsten, tantalum, etc. and alloys thereof The anti-reflective coating layer 38 deposited on top of the metal layer can be a conventional coating material such as titanium tungsten or titanium nitride.
In a conventional deposition process for oxide, a plasma enhanced TEOS (PE TEOS) oxide layer 42 is first deposited on top of the interconnects 34 and the BPSG layer 36 on the silicon substrate. Only a thin layer of PE TEOS oxide layer is usually deposited. In the next step of the oxide planarization process, as shown in FIG. 3C, a thick layer of oxide 46 is deposited on top of the PE TEOS oxide layer 42 by a low temperature deposition process. It is seen in FIG. 3C, the surface obtained after the oxide deposition has a large step height and a poor uniformity in the thickness of the oxide layer formed. It is therefore a poor planarization process. The poor surface planarization obtained, shown in FIG. 3C, results in a poor quality of the wafer that is obtained due to the non-uniformity in the thickness of the oxide layer deposited. This is sometimes referred to as a donut formation on the surface of the wafer since at the wafer idle region, only poor oxide coverage is obtained. The poor coverage of oxide leads to a lower density film that has voids and porosity problem. The non-uniform coverage of the oxide layer on the wafer leads to a high scrap rate of the IC dies that are severed from the wafer. A lower throughput rate usually results from such an oxide deposition process.
It is therefore an object of the present invention to provide a method of forming a planarization layer of an oxide on a semiconductor device that does not have the drawbacks and shortcomings of a conventional oxide deposition processes.
It is another object of the present invention to provide a method of forming a planarization layer of an oxide on a semiconductor device that is capable of producing a device that has a substantially uniform thickness of oxide coated on top.
It is a further object of the present invention to provide a method of forming a planarization layer by an oxide deposition technique such that the occurrence of voids or porosity in the oxide film can be minimized.
It is still another object of the present invention to provide a method of forming a planarization layer of an oxide that does not require extensive changes to be made in the fabrication process.
It is another further object of the present invention to provide a method of forming a planarization layer of an oxide by first depositing a layer of a silicon-rich oxide material on top of the device prior to the forming of metal interconnects.
It is yet another object of the present invention to provide a method of forming a planarization layer of an oxide by first depositing a layer of silicon oxide on the device by a PECVD SiH.sub.4 method or a PECVD TEOS-N.sub.2 O method.
It is still another further object of the present invention to provide a semiconductor structure that has a substantially smooth planarization layer of TEOS-ozone oxide deposited on top.